This application relates to integrated circuits and particularly to integrated circuits such as non-volatile memories that are in communication with a controller via one or more signal lines.
Integrated circuits including various memory devices may be connected together via conductive lines or traces. Integrated circuits may be connected together within a package in some examples. Examples of such connections may be found in non-volatile memory products. There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. A memory controller, usually but not necessarily on a separate integrated circuit chip, interfaces with a host to which the card is removably connected and controls operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during the programming and reading of data. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. Besides the memory card implementation, this type of memory can alternatively be embedded into various types of host systems.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343,063, 5,661,053 and 6,222,762. These patents, and all patents and published patent applications referenced in this application, are incorporated by reference in their entirety.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, and 6,522,580.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride.
As in many integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM memory cell arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage unit or element. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per storage element, and so on. Memory arrays that use such multi-level logic are particularly vulnerable to corruption of data from small changes in stored charge. Selected portions of a multi-state memory cell array may also be operated in two states (binary) for various reasons.
Memory cells of a typical flash EEPROM array are divided into discrete blocks of cells that are erased together. That is, the block is the erase unit, a minimum number of cells that are simultaneously erasable. Each block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in parallel in different sub-arrays or planes. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which they are stored. Such memories are typically configured with 16, 32 or more pages within each block, and each page stores one or just a few host sectors of data.
In order to increase the degree of parallelism during programming user data into the memory array and reading user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips. Examples of such a memory implementation are described in U.S. Pat. Nos. 5,798,968 and 5,890,192.
To further efficiently manage the memory, blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one block from each plane. Use of the metablock is described in international patent application publication no. WO 02/058074. The metablock is identified by a host logical block address as a destination for programming and reading data. All blocks of a metablock may be programmed at the same time. The unit of programming of such a metablock is a metapage, which consists of one page from each block of the metablock. Similarly, all blocks of a metablock are erased together. In some examples, metablock size is fixed so that the metablock is the minimum unit of erase and the metapage is the minimum unit of programming. The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory cell array. Individual pages within the blocks are typically identified by offsets within the block address. Address translation often involves use of intermediate terms of a logical block number (LBN) and logical page.
One or more registers may be used to move data into and out of a memory cell array. Examples of a multiple register memory systems are described in U.S. Pat. Nos. 6,349,056 B1 and 6,560,143 B2. A register typically holds data equal to the data in one row of the memory cell array. A register is generally volatile and therefore any data in such a register is lost if there is a loss of power. A register may be used as a buffer or cache to hold data that is to be programmed to the memory array, or data that is to be sent to a host.
A memory system generally has a controller. A controller may include a microprocessor or micro-controller that is connected through controller interface logic to internal memories and interfaces with external components. A program memory stores the firmware and software accessed by the micro-controller to control the memory system operation to read data from the connected memory units and transmit that data to the host, to write data from the host to the memory chip(s), and to carry out numerous other monitoring and controlling functions.
Integrated circuits are typically formed on a semiconductor substrate by a series of processing steps. The substrates are then divided into individual integrated circuit chips (“die” or “chips”), which may be individually packaged. Alternatively, chips may be packaged so that more than one chip is in a package. For example, two or more memory chips may be packaged together to provide increased memory capacity within a single package. This may provide a cheaper alternative to using separate packages or forming a larger memory on a single chip. Packaging may be by conventional chip packaging methods where chips are encapsulated within a protective shell and pads on the chips are electrically connected to pins on the package to allow communication with the chips. Memory chips packaged in this way may be used in various applications including non-volatile memory systems. Such systems typically include a controller, which may be formed on a separate chip and may be separately packaged.
FIG. 1 shows an example of a memory system including a controller and multiple memory units. The controller is in communication with a host. The memory system of FIG. 1 may be in a memory card such as the commercially available flash memory products previously described. In some examples, each memory unit is separately packaged and the packages are connected to the controller. In other examples, the controller and memory units may be packaged together in a single package. In other examples, two or more memory units may be packaged together and the package thus formed is connected to the controller, which is in a separate package. In flash memory cards, individual packages may be mounted to a printed circuit board, which provides connecting lines between the pins of different packages. It is generally desirable to reduce the number of such lines because they add to the cost and complexity of the memory system. Therefore, when multiple chips are packaged together, they may share a single pin on the package and thus share a single line for communication with the controller.
FIG. 2 shows an example of a memory system having a controller chip in one package (package 1) in communication with two memory chips (memory unit 1 and memory unit 2) in a second package (package 2). Here, each memory unit is formed on an individual memory chip. Thus, memory unit 1 is formed on memory chip 1 and memory unit 2 is formed on memory chip 2. Both memory units 1 and 2 have ready/busy outputs that are connected to a common ready/busy pin on package 2. This common pin connects to the controller chip via a common ready/busy signal line. Though not shown, many other connections may exist between package 1 and package 2. The ready/busy pin is shared to reduce the pin count of both packages and thus reduce the cost and complexity of the system. One problem of such a system is that the ready/busy signal received by the controller may only indicate that one of the memory units is busy, but not which one. Thus, when a busy signal is received, it is not known which memory unit is busy or if one memory unit is ready.
Typically, a high voltage on the signal line may indicate that the integrated circuit is ready, while a low voltage indicates that it is busy. In certain examples, it may be desirable to know more information than just the condition of the integrated circuit as a whole. For example, in memory units having a cache connected to a memory array, it may be useful to know both the condition of the memory array and the condition of the cache. With a single ready/busy signal, this information may not be available to the controller.
FIG. 3 shows an example of a memory unit having a memory array and two registers, a cache (master data register) and a buffer (slave data register). The memory array and connected registers may be considered to be a buffered memory array because both registers serve a buffering function. In addition, this memory unit has a memory control circuit that is in communication with a controller. Communication with the controller takes place over a group of lines that may include a chip enable (CE) line, command latch enable (CLE) line, address latch enable (ALE) line, write enable (WE) line, read enable (RE) line, a set of input/output (I/O) lines and a ready/busy (RIB) line. This memory unit may be packaged individually or with other memory units. In general, a memory unit such as the one shown in FIG. 3 is formed on a dedicated memory chip so that one chip has one memory unit including a memory array and a memory control circuit. Host data from the controller may be sent by the memory control circuit to the cache, then to the buffer and then to the flash memory array. This allows host data to be loaded into the cache at the same time that other data are programmed from the buffer to the flash memory array. This parallelism may speed up data transfer to the flash memory array. However, a ready/busy signal from such a system may only provide one bit of data. The signal may represent that the array is in a first condition such as array busy, or a second condition such as array ready. However, it may be useful to know additional information such as whether the cache is busy or not.
Therefore, there is a need for a control system that allows more information to be provided to the controller along a single line. There is also a need for a system to be configurable by the controller. There is also a need for a system that would allow a controller to determine a condition of an individual integrated circuit that shares a ready/busy line with other integrated circuits.